In digital communications, traditionally, the jitter and phase noise profile of a electronic component such as a Phase Locked Loop (PLL) is measured using spectrum analyzers. Spectrum analyzers are bulky and expensive equipment making them cumbersome to use during chip level production in a digital production test environment. Other measurement suggestions include using Time-to-Digital Converters (TDCs) to measure phase differences; however, TDCs tend to have resolutions in the order of pico-seconds which limits their use only to electronic components (PLL) considered slow for telecommunications purposes and therefore are unsuitable to characterize extremely low jitter PLLs currently being manufactured (˜100 fs).
There is a need to improve jitter and phase noise measurement in a digital test environment for a variety of components.